1. Field of the Invention
The present invention relates to a power semiconductor device having a potential difference along a substrate surface, and more particularly, to a power semiconductor device capable of preventing variations or deterioration in breakdown voltage and a technique related thereto.
2. Description of the Background Art
Power semiconductor devices are generally required to have the function of maintaining the resistance to a high voltage. Among power semiconductor devices having such function, those having the structure of guard rings arranged almost annularly around a certain device or that of a field plate are known as disclosed in Japanese Patent Application Laid-Open Nos. 11-145466 and 9-186315, for example.
FIG. 59 shows an example (First background art) in which the guard ring structure is applied to an IGBT (Insulated Gate Bipolar Transistor), and FIG. 60 shows an example (Second background art: e.g., Japanese Patent Application Laid-Open No. 7-326744) in which the field plate structure is applied to an IGBT. Elements having the same functions are designated by the same reference numerals in FIGS. 59 and 60.
FIG. 59 according to the first background art illustrates: a p+ collector 1; an n+ buffer layer 2; an n− drift layer (substrate) 3; a channel dope 4; an n+ emitter 5; a gate oxide film 6; a polysilicon gate electrode 7; an interlayer insulation film 8; an emitter electrode 9; a p+ isolation well 10; a field oxide film (insulation film) 11; a polysilicon gate electrode 12; a gate electrode 13; guard rings 14a to 14d for maintaining breakdown voltage arranged almost annularly around a transistor containing the channel dope 4, n+ emitter 5, gate oxide film 6, polysilicon gate electrode 7, interlayer insulation film 8, emitter electrode 9 and p+ isolation well 10; A1 electrodes 15a to 15d for grounding the guard rings 14a to 14d; a channel stopper 16; a polysilicon plate 17; a channel stopper ground electrode 18; and a passivation film 19.
The guard ring structure according to the first background art shown in FIG. 59 is provided with the guard rings 14a to 14d to extend a depletion layer such that intensification of an electric field at an edge of the junction of the p+ isolation well 10 and the n− drift layer 3 does not cause deterioration in breakdown voltage, thereby maintaining breakdown voltage.
In the field plate structure according to the second background art shown in FIG. 60, a field plate 20 is appropriately set at a potential lower than that of the main surface of the n− drift layer 3 to extend a depletion layer so as to relax an electric field at the junction of the channel dope 4 and the n− drift layer 3, thereby maintaining breakdown voltage.
The aforementioned first background art has a disadvantage in that breakdown voltage deteriorates under the influence of a chip interface. When voltage is applied across the p+ collector 1 in the state that the upper surface of the chip is sealed with a transfer mold 21 as shown in FIG. 61, for example, movable charges inside the mold 21 causes polarization in the mold, generating negative polarization charges 22a on the side of the channel stopper 16 being almost equal in potential to the p+ collector 1 and positive polarization charges 22b on the emitter side. This affects regions 23a to 23c of low concentration of the substrate surface (i.e., part of the n− drift layer 3 interposed between the guard rings 14a to 14d, respectively), resulting in variations in breakdown voltage as a whole and, in a worse situation, resulting in surface inversion, which may cause significant deterioration in breakdown voltage.
The second background art also has a disadvantage in that mold polarization may affect a region between the polysilicon gate electrode 12 and the polysilicon plate 17, resulting in variations or deterioration in breakdown voltage.
A third background art has been proposed against the first background art shown in FIG. 59 and the second background art shown in FIG. 60, in which the use of a semi-insulation film as the passivation film 19 on the chip surface at the expense of insulation properties to some degree allows hopping conduction of charges inside the semi-insulation film with heat energy or the like, causing the polarization charges 22a and 22b in the mold 21 to be cancelled out by the charges inside the passivation film 19, which can reduce the influence exerted upon the surface of the n− drift layer 3.
In the third background art, however, the passivation film 19 is basically required to serve as an insulation film, imposing limitations on the conductivity of the semi-insulation film. This causes a disadvantage that the above-described cancel-out effect of charges in the passivation film 19 has limitations, producing little effect on strong polarization in the mold 21 over the passivation film 19. Of course, increasing the conductivity of the passivation film 19 improves the cancel-out effect of charges, which, however, disadvantageously increases leakage current.
Further, CVD nitride films generally known as semi-insulation films disadvantageously affect electric properties of polysilicon elements including polysilicon of low concentration. Generally, a nitride-film-based semi-insulation film is formed by CVD or the like, at which hydrogen is produced as a product of a chemical reaction in the film deposition. Hydrogen produced at this time passivates dangling bonds of the surface of polysilicon with voltage bias or the like, resulting in changes in electric properties of the polysilicon surface. The reason why such changes in electric properties of polysilicon surface have not become a serious problem in the field of power devices is that polysilicon devices have generally been used only for polysilicon devices of a greatly high concentration such as gate wiring and have had low sensitivity to variations in electric properties at the interface. However, recent power devices are being improved in integration of circuit elements for improved performance, increasing the necessity to achieve integration of polysilicon elements. Therefore, the problem of changes in electric properties of polysilicon surface is becoming evident.
Furthermore, the influence of polarization becomes significant in the structure having a high potential only in part of the outer peripheral portion as shown in FIGS. 62 to 65 as a fourth background art. FIG. 62 is a plane view of a power semiconductor device, and FIG. 63 is a partially enlarged plane view thereof. FIGS. 64 and 65 are cross-sectional views taken along the lines A—A and B—B of FIG. 62, respectively.
As shown in FIGS. 62 to 65, a polysilicon Zener diode 27 for overvoltage protection is provided between the channel stopper 16 serving as a collector and the gate electrode 12 and is connected to the gate electrode 12 at its inner periphery and to the channel stopper 16 at its outer periphery. When the influence of polarization in a mold (cf. 21 in FIG. 61) over the passivation film 19 is negligible, the guard rings 14a to 14d and the diode 27 are designed to be matched in potential, causing no deterioration in breakdown voltage at the guard rings 14a to 14d and the diode 27.
However, when polarization occurs in the mold 21 over the passivation film 19 as described above and the surface of the n− drift layer 3 is inverted, the potential distribution inside the n− drift layer 3 varies, causing the polysilicon gate electrode 12 and the polysilicon plate 17 to be unmatched in potential, which disadvantageously causes deterioration in breakdown voltage.
Further, since the polysilicon Zener diode 27 itself has a polysilicon region of low concentration, the use of a semi-insulation film for the passivation film 19 as in the third background art causes variations in breakdown voltage of the diode 27 itself.